In the NASA funded Phase II SBIR titled "Rad-Hard and ULP (ultra low power) FPGA with "full functionality", RNET will be designing and fabricating an innovative device using a double-gate process from ASI (American Semiconductor Inc.). The FPGA will include a variety of features including programmable logic, softcore microprocessor, dedicated DSP functions, I/O, dedicated memory blocks, memory controllers, global clock, and JTAG interface.
In the Air Force funded Phase II SBIR, RNET will develop a high-speed fault-tolerant ROIC (read-out integrated circuit) in collaboration with L3 Com - CE.
In the two Phase I STTRT projects (one funded by AFOSR) and the other funded by DOE, RNET will optimizing CFD code for modern compute and GPU architectures. The Air Force funded STTR focuses on AVUS CFD code, while the DOE funded STTR focuses on CFD models for Catalytic Converters.
Further details are provided in the Projects section.